The present invention generally relates to methods for performing failure analysis of semiconductor memory, and more specifically relates to a method for performing logical to physical verification of semiconductor memory by intentionally creating an electrical design “defect” within the physical representation of a design layout.
During the failure analysis of semiconductor memory, it is necessary to know the physical location of a failing memory bit, but typically what is available from the design is merely the design logical representation of the failing bit. Once the logical location is determined, a scramble equation is used to identify the physical location of the failing bit, based on the logical location. As such, the scramble equation effectively converts the logical location to the physical location of the failing bit. However, often there are errors in the scramble mapping. As a result, there is a need to physically verify that the determined physical location is correct. If this verification is not performed, then failure analysis will subsequently be performed on the incorrect memory location, incurring extra delays and costs.
Currently, the typical method to verify that the calculated physical location is correct is to use a focused ion beam (FIB) to physically damage that particular memory location and then retest it. FIG. 1 provides a flow diagram which illustrates the typical method in more detail. As shown, the process is started (bubble 100 in FIG. 1) and initially a package unit, such as a flip-chip package, is decapped (block 102 in FIG. 1). Then, design layout CAD files are accessed to identify circuitry in the memory area of interest (block 104 in FIG. 1). Then, a focused ion beam (FIB) and the CAD software are used to navigate through the backside of the silicon and physically damage the identified location (block 106 in FIG. 1). Subsequently, electrical verification is performed on the Automated Test Equipment (ATE) to confirm that the electrical address matches the physical site which was damaged using the focused ion beam (block 108 in FIG. 1). If the electrical results indicate that the electrical address matches the physical site which was damaged (diamond 110 in FIG. 1), the process is ended (bubble 112 in FIG. 1). Otherwise, the focused ion beam (FIB) and the CAD software are used to navigate through the backside of the silicon and physically damage another location (block 106 in FIG. 1), and electrical verification is again performed on the Automated Test Equipment (ATE) to confirm that the electrical address matches the physical site which was damaged using the focused ion beam (block 108 in FIG. 1), and so on.
The disadvantages of using a focused ion beam to physically damage memory locations in order to verify that a calculated physical location matches a design logical representation include, but may not be limited to, the following: the process is costly; it takes a long time to make the focused ion beam cut, and the focused ion beam is typically a limited availability tool; the package trend for complex ASIC designs is to use flip-chip packaging, and using a focused ion beam to navigate through the backside of the silicon and physically damage a memory location is difficult and may require several attempts; and if the electrical re-test result does not correspond with the damaged location, then this operation may be required to be repeated over several iterations (and possibly several new units) causing costly delays and engineering resources.